The present invention relates to a semiconductor integrated circuit having a booster circuit constructed by a charge pump circuit and, more particularly, to a technique useful to reduce a chip occupying area of the booster circuit.
In a booster circuit constructed by a charge pump circuit, as described in Japanese Unexamined Patent Publication No. 2005-57860, a high-side switch for precharge and a low-side switch for precharge are connected to one end and the other end of a capacitor, respectively, and a high-side switch for driving output and a low-side switch for driving output are connected to the other end and the one end of the capacitor, respectively. The four transistors as four switches are driven by clock signals. The period of one of levels of the clock signal is a precharge period in which the booster circuit constructed by a charge pump circuit charges the capacitor with an input voltage to be boosted. The period of the other level of the clock signal is an output driving period in which the booster circuit constructed by a charge pump circuit outputs a boosted voltage obtained by adding a charge voltage of the capacitor to the input voltage. In the precharge period, the high-side switch for precharge connected between the input voltage and the one end of the capacitor is on, and the low-side switch for precharge connected between base potential (ground potential) and the other end of the capacitor is on. Therefore, the charge current flows from the input voltage to the base potential (ground potential) via the capacitor, so that the charge voltage between the one end of the capacitor and the other end increases. In the output driving period, the high-side switch for driving output connected between the input voltage and the other end of the capacitor is on, and the low-side switch for driving output connected between the one end of the capacitor and the output terminal is on. Therefore, the boosted voltage obtained by adding the charge voltage of the capacitor to the input voltage is output from the output terminal. The clock signal changes repeatedly in the sufficient number of cycles between one of the levels and the other level, thereby increasing the charge voltage of the capacitor to the input voltage. Consequently, the boosted voltage from the output terminal is about twice as high as the input voltage.